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Philips
Senior Analog IC-Design Engineer
Project is closed
Posted
Mar 13, 2020
Project ID:
PHILJP00019988
Location
Eindhoven, Noord Brabant
Hours/week
40 hrs/week
Timeline
1 year
Starts: Jul 1, 2019
Ends: Jul 1, 2020
Payrate range
0 - 72 €/hr
Senior Analog IC-Design Engineer
Project description:
At Philips Research a project is ongoing for the design of a mixed-signal IC for biomedical applications.
The SOI-CMOS IC includes analog, digital and mixed-signal circuits. The candidate will contribute to thedesign of this IC.
Requirements:
The candidate must meet the following minimum requirements:
- At least five years of experience in analog circuit design, simulation and layout using Cadence. Designing circuits such as amplifiers, buffers, current sources, etc.
-Understanding of CMOS technologies in general: working with design rules, understanding process specification documents.
-Creating simulation test-benches for dc, ac, transient simulations using ADE-L and ADE-XL.
-Understanding low-noise analog circuit design.
-Familiar with CMOS technologies at various technology nodes such as 180nm to 40nm.
-Experience with SOI-CMOStechnologies is beneficial.
-Basic knowledge of MatLab. Experience with Cadence-MatLab co-simulation is a plus.
-Experience with full-custom IC layout design using Cadence tools Virtuoso, Layout-XL, DRC and LVS.
-Understanding and implementing layout techniques such as symmetry and shielding.
-Creating layout designs according to a floorplan.
-Basic understanding of Unix.
-Team player: daily interaction with designteam.
-Reporting progress and issues.
-Fluent in English.
-Experience with mixed-signal design and verification using AMS is a plus.
-Basic knowledge of digitaldesign / Encounter is beneficial.
Project description:
At Philips Research a project is ongoing for the design of a mixed-signal IC for biomedical applications.
The SOI-CMOS IC includes analog, digital and mixed-signal circuits. The candidate will contribute to thedesign of this IC.
Requirements:
The candidate must meet the following minimum requirements:
- At least five years of experience in analog circuit design, simulation and layout using Cadence. Designing circuits such as amplifiers, buffers, current sources, etc.
-Understanding of CMOS technologies in general: working with design rules, understanding process specification documents.
-Creating simulation test-benches for dc, ac, transient simulations using ADE-L and ADE-XL.
-Understanding low-noise analog circuit design.
-Familiar with CMOS technologies at various technology nodes such as 180nm to 40nm.
-Experience with SOI-CMOStechnologies is beneficial.
-Basic knowledge of MatLab. Experience with Cadence-MatLab co-simulation is a plus.
-Experience with full-custom IC layout design using Cadence tools Virtuoso, Layout-XL, DRC and LVS.
-Understanding and implementing layout techniques such as symmetry and shielding.
-Creating layout designs according to a floorplan.
-Basic understanding of Unix.
-Team player: daily interaction with designteam.
-Reporting progress and issues.
-Fluent in English.
-Experience with mixed-signal design and verification using AMS is a plus.
-Basic knowledge of digitaldesign / Encounter is beneficial.
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