Senior Analog/Mixed-Signal ASIC Design Engineer (Freelance)
At Philips Research a project is ongoing for the design of a mixed-signal ASIC for biomedical applications.
The 40nm CMOS IC includes analog, digital and mixed-signal circuits. The candidate will contribute to the design of this IC.
The candidate must meet the following minimum requirements.
- At least five years of experience in analog circuit design, simulation and layout using Cadence.
- Designing circuits such as amplifiers, buffers, samplers, current sources, etc.
- Understanding of CMOS technologies in general: working with design rules, understanding process specification documents.
- Creating simulation test-benches for dc, ac, transient simulations using ADE-L and ADE-XL.
- Understanding low-noise analog circuit design.
- Familiar with CMOS technologies at various technology nodes such as 180nm to 40nm.
- Experience with ADC and/or DAC design is beneficial.
- Experience with mixed-signal design and verification using AMS is a plus.
- Basic knowledge of digital design/ Encounter is beneficial.
- Experience with full-custom IC layout design using Cadence tools Virtuoso, Layout-XL, DRC and LVS.
- Understanding and implementing layout techniques such as symmetry and shielding.
- Creating layout designs according to a floorplan.
- Basic understanding of Unix.
- Team player: daily interaction with design team.
- Reporting progress and issues.
- Fluent in English.
Location: High Tech Campus, Eindhoven for at least the first month. Remote working optional depending on project and progress
Schedule: Preferably full-time or at least 4 days/week
Duration: 6 months initially