Philips
Digital ASIC Design and Verification Engineer
Digital ASIC Design and Verification Engineer
Philips Medical Systems is seeking a Digital ASIC Design and Verification Engineer to join our dynamic team. Our ASIC team focuses on the design of mixed-signal Application-Specific Integrated Circuits (ASICs) for biomedical applications, with a particular emphasis on CMOS ASICs that handle sensor interfacing functions with a significant digital component. In this role, you will play a crucial part in a project centered around an innovative application, taking charge of designing and verifying digital systems and sub-systems alongside digital architects, back-end engineers, and FPGA engineers.
Initial Contract Duration: 1 year
Full-time Starting date: ASAP
Responsibilities:
Develop and maintain digital designs for ASIC implementation.
Create comprehensive test plans and collaborate with stakeholders for agreement.
Perform verification from block level to top level for digital components of the ASIC.
Develop and maintain test scripts to automate the verification process.
Conduct verification across process corners and with post-layout designs.
Assist mixed-signal verification engineers.
Collaborate on existing designs and contribute to improvements where necessary.
Report progress and issues to the team lead/project leader and customer.
Conduct FPGA prototyping as needed.
Assist with silicon validation activities.
Requirements:
University Degree (Master’s or Bachelor’s) in Electrical Engineering.
Minimum of five years experience in digital design and verification.
Proficiency in verbal and written English.
Strong grasp of digital ASIC design flows, spanning from system architecture to RTL and Post-layout.
Proficiency with VHDL/Verilog/SystemVerilog/UVM and Cadence tools.
Ability to develop and execute test plans, debug, and analyze potential issues during verification.
Experience with co-simulation of digital and analog IPs for verifying mixed-signal systems.
Familiarity with integrating IP blocks such as memories, dual-port memories, and OTP.
Experience with high-speed interfacing at Gb/s speeds is advantageous.
Knowledge of scan chain insertion and verification.