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Digital ASIC Architect, Team Lead (Freelance)
Project is closed
Posted Sep 6, 2022
Project ID: PHILJP00025357
Eindhoven, Noord Brabant
(Oct 3, 2022 - Sep 30, 2023)
67 - 90 €/hr
Application Deadline: Oct 3, 2022 12:00 PM
At Philips Research in the group of IGT and Ultrasound Devices & Systems, the ASIC team is working on the design of various mixed-signal Application-Specific ICs (ASIC) for biomedical applications. These CMOS ASICs usually perform sensor interfacing functions with a significant digital content. The candidate will take part in the design of an ASIC for a novel and exciting application, leading a team of digital designers, working closely together with an analog and mixed-signal team.
The candidate must meet the following minimum requirements:
- Has University Degree (Master or Bachelor) in Electrical Engineering.
- At least ten years of experience in digital system architecture, design,
verification and physical implementation. Is able to improve existing solutions.
- Solid understanding of the digital ASIC design flows, from system architecture to RTL, digital and mixed signal verification, design synthesis, physical implementation, and timing analyses.
- Comprehensive knowledge of VHDL, system Verilog and preferably python.
- Being able to specify, evaluate and integrate IP blocks such as memories.
- Familiar with DFT including test-pattern generation.
- Lead the digital team of front-end, back-end and verification engineers while contributing to the design.
- Support the team to optimize progress.
- Working with analog and mixed-signal teams on a daily basis.
- Participating in system verifications using Cadence AMS tools.
- Reporting progress and issues to the project leader and customer.
- Fluent in English.
- Experience in IC realization of DSP algorithms and functions for sensor interfacing applications, including digital filters, sample rate converters and communication protocols preferred.
- Experience with mixed-signal design and AMS verification, UVM verification is a plus.
- Basic knowledge of Mentor Graphics HDL Designer and Questasim and Cadence Virtuoso for analog design is beneficial.
- Hands-on experience in digital backend is a big advantage.
Location: High Tech Campus, Eindhoven
Initial Contract Duration: 1 year, full-time
Starting date: October 2022
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